1. Field of the Invention
The present invention relates to a semiconductor memory device and to a method of manufacturing the same, particularly to a semiconductor memory device having a switch MOS transistor, and a charge accumulating capacitor.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is a known semiconductor memory device having a switch MOS transistor and a charge accumulating capacitor. In order to satisfy the recent requirements for high integration a DRAM has been developed that has a stacked type capacitor structure for accumulating charges.
FIG. 43 is a cross section showing a DRAM having conventional a stacked type capacitor. Referring to FIG. 43, the DRAM includes a memory cell array provided with memory cells which include switch MOS transistors and charge accumulating capacitors, and a peripheral circuitry provided with peripheral circuits for controlling operation of the memory cells.
A p-type silicon substrate 1 is selectively provided at its main surface with element isolating oxide films 2. The memory cell array is provided with switch transistor pairs 5, only one of which is shown in FIG. 43. Switch MOS transistor pair 5 includes n-type impurity diffusion regions 6a, 6b and 6c, which are formed at the main surface of silicon substrate 1 and are spaced from each other to define channel regions, as well as gate electrodes 4 formed on the channel regions with gate oxide films 3 therebetween.
Each gate electrode 4 is covered with an oxide film 7. Over element isolating oxide films 2, there are extended word lines 4 connected to gate electrodes of another switch MOS transistors. In the peripheral circuitry, an n-type impurity diffusion region 6d is formed at the main surface of p-type silicon substrate 1.
Gate electrodes 4 and oxide films 7 are covered with a first interlayer insulating layer 8 which is made of, e.g., a silicon oxide film and is formed on the main surface of p-type silicon substrate 1. Interlayer insulating layer 8 has a thickness not less than about 3000. First interlayer insulating layer 8 is provided with a contact hole 9 reaching n-type impurity diffusion layer 6b. A bit line 10 is formed in contact hole 9. In this case, bit line 10 has a polycide structure including a polycrystalline silicon layer and a silicide layer formed on this polycrystalline silicon layer.
Bit line 10 and first interlayer insulating layer 8 are covered with a second interlayer insulating layer 11 formed of, e.g., a silicon oxide film. There are also formed contact holes 25 which penetrate second and first interlayer insulating layers 11 and 8 and reach n-type impurity diffusion layers 6a or 6c.
A capacitor lower electrode 13 made of polycrystalline silicon is formed in each contact hole 25 and extends over second interlayer insulating layer 11. Capacitor lower electrode 13 is covered with a capacitor dielectric film 14 having a layered structure formed of a silicon nitride film and a silicon oxide film. Capacitor dielectric film 14 is covered with a capacitor upper electrode 15 made of, e.g., polycrystalline silicon. Capacitor lower electrode 13, capacitor dielectric film 14 and capacitor upper electrode 15 form a capacitor 12 for accumulating electric charges.
Capacitor 12 is covered with a third interlayer insulating layer 16 which is formed of, e.g., a silicon oxide film and extends from the memory cell array into the peripheral circuitry. In the memory cell array, there are formed gate electrodes 4 of switch transistors 5 and capacitor 12 as described above, so that the upper surface of third interlayer insulating layer 16 is located at a level higher than the upper surface of third interlayer insulating layer 16 in the peripheral circuitry. As a result, a stepped portion 20 is formed at and around a boundary between the peripheral circuitry and the memory cell array.
On third interlayer insulating layer 16, there are formed interconnection layers 17 made of material including aluminum or the like. As shown in FIG. 43, interconnection layer 17 may be formed on stepped portion 20. In this case, contact hole 18 which extends through first, second and third interlayer insulating layers 8, 11 and 16 to n-type impurity diffusion layer 6d is formed at the peripheral circuitry near the memory cell array, and a plug electrode 19 made of, e.g., tungsten is formed in contact hole 18. Plug electrode 19 electrically connects interconnection layer 17 formed on stepped portion 20 to n-type impurity diffusion layer 6d.
However, the conventional DRAM described above has the following problems, which will be described below with reference to FIGS. 43 and 44. FIG. 44 is a cross section showing, on an enlarged scale, the peripheral circuitry and the memory cell array in FIG. 43.
As shown in FIG. 43, the memory cell array is provided with capacitor 12, bit line 10 and gate electrode 4 of switch MOS transistor 5. Meanwhile, these are not formed in the peripheral circuitry. As a result, stepped portion 20 having a large level difference H is formed at the boundary between the memory cell array and the peripheral circuitry as shown in FIG. 44. This reduces a focus margin in an exposure process for patterning which will be performed for forming interconnection layers 17, when interconnection layer 17 is to be formed on the stepped portion 20. This presents difficulty in formation of interconnection layers 17. Further, the large level difference H is liable to cause failure in patterning of interconnection layers 17. Therefore, problems such as breakage of interconnection layer 17 and/or short-circuit between adjacent interconnection layers 17 are liable to occur.
Further, if contact hole 18 is formed at stepped portion 20 having the large level difference H as described above, contact hole 18 has a depth D considerably larger than that of other contact holes, i.e., contact holes formed inside the peripheral circuitry. This results in deviation of the depth of contact holes in the peripheral circuitry. This presents difficulty in formation of the contact holes in the peripheral circuitry. Further, due to the large depth D of contact hole 18, a void is liable to generate at plug electrode 19, which is formed in contact hole 18. This reduces reliability of the interconnection layers.